The present invention relates to the structure of transistor cells for semicustom chips.
The semicustom method of designing and fabricating integrated circuits uses prefabricated semiconductor wafers which have completed circuits except for the final process step of device or component interconnection. A cost savings is realized by adapting a standard wafer, which has already been designed and manufactured, to a particular customer's needs by simply designing appropriate metal interconnections. Thus, for each customer, a metal mask is designed which connects the necessary active and passive semiconductor components to form the circuit configuration required by the customer. This method of design and fabrication allows development of a custom circuit in less time and at lower cost than if the entire wafer had to be independently designed for each customer.
A limitation in semicustom design is that the polarity and number of transistors is fixed in the prefabricated wafer and cannot be changed at the metal mask level. Thus, for instance, if the standard wafer has more NPN transistors than a particular customer needs in a circuit, these transistors will be unused and waste valuable space on the wafer. In addition, the routing of the metal interconnections may be difficult and inefficient because a PNP transistor is located at a position where the customer's circuit would ideally require an NPN transistor, or vice versa. The usefulness of a prefabricated wafer is thus limited to circuits which require the approximate number, polarity and location of transistors which are on the standard wafer.
The devices on a standard wafer are formed in a number of cells which contain one or more devices which form the building blocks of a customer's circuit. An example of a typical known cell 10 having a single PNP transistor is shown in FIG. 1. A P-doped isolation well 12 in an epitaxial (EPI) layer 14 defines a border for the cell and isolates it from other devices. A central P- doped region 16 forms the emitter of the transistor with a pair of L shaped P-doped regions 18 forming the collector of the transistor and an N-doped region 20 forming the base of the transistor. This design may vary, but in general base 20 is off to a side while the central emitter 16 is partially surrounded by the collector 18.
FIG. 2 shows an example of a typical known cell 22 for an NPN transistor. A P-doped isolation region 24 in an epitaxial region 26 surrounds cell 22. An N-doped region 28 forms the collector of the transistor and a P-doped region 30 forms the base of the transistor. An N-doped region 32 within P-doped base region 30 forms the emitter of the transistor.
In a semicustom chip, the PNP and NPN transistors of FIGS. 1 and 2 may both be on the same semiconductor wafer, with one or the other being connected as required by the customer's circuit. If there are more of either the PNP or the NPN transistors on the chip than are required by the customer's circuit, the space taken up by all such transistors will be wasted. Some savings of space may be achieved by combining several transistors in a single cell, usually two PNP or two NPN transistors in a cell or, less often, a PNP and an NPN transistor in a single cell. Although the spacing in between cells is thus reduced, the size of the cell is increased by the size of the additional transistors added.
There is thus a need in semicustom chip design for a transistor cell which contains both NPN and PNP transistors but which does not take up the area of two separate NPN and PNP transistors.